Figure 12(a) shows a steady state switching circuit of a power MOSFET. When a pulse input voltage is applied to the gate of power MOSFET, the device will be turn-on if the gate to source voltage V_GS is greater than threshold voltage V_GS(th). The switching waveforms of a power MOSFET are illustrated in Figure 12.

At time t = t₀, input voltage at the gate of power MOSFET is Vg = 0 and the gate to source voltage V_GS is less than threshold voltage V_GS(th). At that moment, the device operates in OFF state and the drain current I_D is equal to zero and the output voltage is V_O = V_DS = V_DD.

At time t = t₁, voltage starts to increase from 0 to V₁ and the input capacitance C_gs starts to charge as depicted in Figure. During the turn on delay time t_d, the capacitance C_gs is charged to gate threshold voltage V_GS(th). During rise time t_r, the gate to source voltage V_GS increases from gate threshold level V_GS(th) to the full gate voltage, V_GSP to operate the transistor in linear region. In time t_r, the drain current increases from 0 to I_D. The total turn on time of MOSFET is sum of delay time and rise time.

1. Delay time t_d The delay time td is the time required to charge the input capacitance from its initial value to gate threshold voltage V_GS(th).
2. Rise time t_r The rise time t_r is the time required to charge the input capacitance Cgs from gate threshold level V_GS(th) to the full gate voltage, V_GSP.
3. Turn-on time t_turn-on The turn-on time is the sum of the delay time t_d and the rise time t_r and it can be expressed as t_turn-on = t_d + t_r.

In the turn-off process, the gate voltage Vg is removed t = t₂, the input capacitance starts to discharge from gate voltage V₁ to V_GSP. V_GS must be decreased significantly so that V_DS starts to increase. The fall time is the time during which input capacitance discharged from V_GSP to gate threshold voltage V_GS(th). In this time, the drain current decreases from I_D to zero. When V_GS<V_GS(th), the device completely turn off.

The turn-off delay time t_df is the time during which the input capacitance discharges from gate voltage V1 to VGSP.

The fall time t_f is the time in which the input capacitance discharges from gate voltage V_GSP to V_GS(th) and the drain current becomes zero.

The turn-off time is the sum of the turn-off delay time (t_df) and fall time (t_f) and it can be represented by t_turn-off = t_df + t_f.

Figure 12