Figure 12(a) shows a steady state switching circuit of a power MOSFET. When a pulse input voltage is applied to the gate of power MOSFET, the device will be turn-on if the gate to source voltage V_{GS} is greater than threshold voltage V_{GS(th)}. The switching waveforms of a power MOSFET are illustrated in Figure 12.

At time t = t_{0}, input voltage at the gate of power MOSFET is Vg = 0 and the gate to source voltage V_{GS} is less than threshold voltage V_{GS(th)}. At that moment, the device operates in OFF state and the drain current I_{D} is equal to zero and the output voltage is V_{O} = V_{DS} = V_{DD}.

At time t = t_{1}, voltage starts to increase from 0 to V_{1} and the input capacitance C_{gs} starts to charge as depicted in Figure. During the turn on delay time t_{d}, the capacitance C_{gs} is charged to gate threshold voltage V_{GS(th)}. During rise time t_{r}, the gate to source voltage V_{GS} increases from gate threshold level V_{GS(th)} to the full gate voltage, V_{GSP} to operate the transistor in linear region. In time t_{r}, the drain current increases from 0 to I_{D}. The total turn on time of MOSFET is sum of delay time and rise time.

- Delay time t
_{d}The delay time td is the time required to charge the input capacitance from its initial value to gate threshold voltage V_{GS(th)}. - Rise time t
_{r}The rise time t_{r}is the time required to charge the input capacitance Cgs from gate threshold level V_{GS(th)}to the full gate voltage, V_{GSP}. - Turn-on time t
_{turn-on}The turn-on time is the sum of the delay time t_{d}and the rise time t_{r}and it can be expressed as t_{turn-on}= t_{d}+ t_{r}.

In the turn-off process, the gate voltage Vg is removed t = t_{2}, the input capacitance starts to discharge from gate voltage V_{1} to V_{GSP}. V_{GS} must be decreased significantly so that V_{DS} starts to increase. The fall time is the time during which input capacitance discharged from V_{GSP} to gate threshold voltage V_{GS(th)}. In this time, the drain current decreases from I_{D} to zero. When V_{GS}<V_{GS(th)}, the device completely turn off.

The turn-off delay time t_{df} is the time during which the input capacitance discharges from gate voltage V1 to VGSP.

The fall time t_{f} is the time in which the input capacitance discharges from gate voltage V_{GSP} to V_{GS(th)} and the drain current becomes zero.

The turn-off time is the sum of the turn-off delay time (t_{df}) and fall time (t_{f}) and it can be represented by t_{turn-off} = t_{df} + t_{f}.

Figure 12

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