Why not avoid all these signal processing architectural issues by using a RISC (reduced instruction set computer) architecture, since RISC seems a solution for so many other problems?
As central processor architectures matured, their Instruction sets became ‘richer’ and more complex. A CISC design includes instructions for basic processor operations, plus single instructions that are sophisticated enough to evaluate a high-order polynomial, for example. But CISC has a price: many of the instructions execute via microcode in the CPU and require numerous clock cycles, plus silicon real estate for code storage.
In contrast, the reduced instruction set computer (RISC) recognizes that in many applications, basic instructions such as LOAD and STORE-with simple addressing modes-are used much more frequently than the advanced instructions, and should not incur an execution penalty. These simpler instructions are ‘hard-wired’ in the CPU logic to execute in a single clock cycle, reducing execution time and CPU complexity.
RISC AND DSP APPLICATIONS
Although the RISC approach offers many advantages in general-purpose computing, it Is not well suited to DSP. For example, most RISCs do not support single-instruction multiplication, a very common and repetitive operation in DSP. The DSP is optimized to accomplish its task fast enough to be ‘real time’ in the context of the application, which requires single-cycle arithmetic operations and accumulations.
DSP algorithms have unique needs not found in general-purpose computing: circular buffering, pointer updating and fast looping with zero overhead, bit reversing, barrel shifting, scaling, and data-dependent execution branching. Each of these should execute with in the DSP instruction, and not as a separate time-consuming instruction cycle. The computational unit within the DSP must be run efficiently, with data arriving from at least two separate data address generators and no. time penalty for data access. CISCs and RISCs support virtually none of these needs.
Software programming also differs. RISCs and CISCs are programmed in high-level languages to minimize software development time and hide the instruction set from the programmer. For DSP, however, code optimization (primarily of execution time, but also of memory usage) requires that the software engineer use assembly language to get the satisfactory performance. Critical sections of the program are examined and recoded if needed, to reduce overall execution time, after simulation and run-time histograms.
In theory, any processor-even a hand-held calculator-can accomplish any software task, given enough time. However, DSPs are optimized for the unique requirements of a real-world signal processing computational needs and algorithms, while CISCs and RISCs are better suited for general-purpose calculations, and where real time is usually not a factor.