Frequency Limits in Digital Integrated Circuits

Published On: August 15, 2014By


Modern digital integrated circuits such as programmable array logic (PALs) and microprocessors are composed of interconnected transistor circuits known as gates. Digital signals are represented symbolically by combinations of ones and zeroes, and can be either data or instructions (such as “add” or “subtract”). Electrically, we represent logic “1” by a “high” voltage and logic “0” by “low” voltage. In practice, there is a range of voltages that correspond to each; for example, in the 7400 series of TTL logic integrated circuits, any voltage between 2 and 5 V will be interpreted as a logic “1”, and any voltage between 0 and 0.8 V will be interpreted as a logic “0”. Voltages between 0.8 and 2 V do not correspond to any logic state.

A key parameter in digital circuits is the speed at which we can effectively use them. In this sense, “speed” refers to how quickly we can switch a gate from one logic state to another (either logic “0” to logic “1” or vice versa), and the time delay required to convey the output of one gate to the input of the next gate. Although transistors contain “built-in” capacitances that affect their switching speed, it is the interconnect pathways that presently limit the speed of the fastest digital integrated circuits. We can model the interconnect pathway between two logic gates using a simple RC circuit (although as feature sizes continue to decrease in modern designs, more detailed models are required to accurately predict circuit performance). For example, consider a 2000-µm-long pathway 2 µm wide. We can model this pathway in a typical silicon-based integrated circuit as having a capacitance of 0.5 pF and a resistance of 100 Ω.

Let’s assume the voltage Vout represents the output voltage of a gate that is changing from a logic “0” state to a logic “1” state. The voltage Vin appears across the input of yet another gate, and we are interested in how long it takes Vin to reach the same value as Vout.

Assuming the 0.5 pF capacitance that characterizes the interconnect pathway is initially discharged [i.e. Vin = 0], calculating the RC time constant for our pathway as τ = RC = 50 ps, and defining t = 0 as when Vout changes, we obtain the expression

Vin (t) = A e–t / τ + Vout (0)

Setting Vin (0), we find that A = – Vout (0) so that

Vin (t) = Vout (0) [1 – e–t / τ]

By examining this equation, we see that Vin will reach the value Vout (0) after 5τ or 250 ps. If the voltage Vout changes again before this transient time period over, then the capacitor does not have sufficient time to charge. In such situations, Vin will be less than Vout (0). Assuming that Vout (0) equals the minimum logic “1” voltage, for example, this means that Vin will not correspond to a logic “1”. If Vout has suddenly changed to 0 V (logic “0”), the capacitor will begin to discharge so that Vin decreases further. Thus, by switching our logic states too quickly, we were unable to transfer the information from one gate to another. The fastest speed at which can change logic states is therefore (5τ)–1. This can be expressed in terms of the maximum operating frequency: fmax = 1 / 2*(5τ) = 2 GHz, where the factor of 2 represents a charge / discharge period. If we desire to operate our integrated circuit at a higher frequency so that calculations can be performed faster, we need to reduce the interconnect capacitance and / or the interconnect resistance.

We should also note that a few minor details were swept under the carpet. First, we assumed a zero rise time for Vout by starting t = 0 at the instant Vout “changes”. In reality, it only needs to reach 2 V to qualify as logic “1” although it may well continue to increase to 5 V. Secondly, as explained in the first paragraph, Vin does not need to reach Vout exactly to represent the logic state.

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